In an out-of-order processor a load instruction may not be safely issued to a memory address before the memory addresses of all of the store instructions preceding the load instruction have been resolved. This is because if a preceding store instruction writes to the memory address read by the load instruction, then the load instruction should read the data written by the store instruction instead of the data in memory to ensure it has the most recent data. However, stalling load instructions until the memory addresses of all preceding store instructions have been resolved causes unnecessary delays.
In some out-of-order processors this issue has been addressed by speculatively issuing load instructions to the memory before the memory addresses of all preceding store instructions have been resolved. If a preceding store instruction is later determined to write to the same memory address as the load instruction then the load instruction is rewound and the correct data used. However, rewinds are complicated and costly and ideally should be avoided.
In some out-of-order processors the number of rewinds has been reduced by predicting whether a load instruction will conflict with a preceding store instruction (e.g. the store instruction will write to the same memory address as the load instruction) based on whether they have conflicted in the past. For example, the program counter may be used to look into a table to determine if the load and the store instructions have conflicted in the past. If they have conflicted in the past then the load instruction may not be issued until the memory address of the store has been resolved. This technique may be useful where the load and store instructions are in a loop and thus are repeatedly executed.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known out-of-order processors.